1. Field of the Invention
The present invention relates to a translation circuit for switching between different logic-level swings. In particular, the present invention relates to a translation circuit for switching between the logic levels associated with Emitter-Coupled-Logic (ECL) circuits and the logic levels associated with Complementary Metal-Oxide-Semiconductor (CMOS) circuits. More particularly, the present invention relates to a translation circuit which generates a reference voltage that provides an ECL-to-CMOS logic level transition with minimal delay.
2. Description of the Prior Art
In the rapidly-expanding field of circuits which take advantage of the desirable characteristics of both bipolar transistors and MOS transistors, it is necessary to provide for smooth and fast transition between the different logic-level voltage ranges associated with the two. Specifically, bipolar transistors, which are well-known as having fast switching rates between logic level high and logic level low, also dissipate power to the extent that they cannot be used exclusively in circuit design. MOS transistors, on the other hand, dissipate little power. For that reason, many MOS transistors can be used in a small area with little regard to overheating. However, MOS transistors are much slower than bipolar transistors with regard to switching between logic levels high and low. The difference in switching speeds is related to the difference in logic-level "swings" associated with the two transistor types. Specifically, MOS transistors swing from rail-to-rail voltage levels, while bipolar transistors have logic level swings that are approximately an order of magnitude less.
In order to take advantage of both the fast switching rates of bipolar transistors and the low power consumption of MOS transistors, one often combines the two types on the same chip to form what is commonly known as BiCMOS circuitry. In this combination it is necessary to confront the difference in the logic level swings associated with the two transistor types so as to resolve the problems which this difference causes. Typically, a bipolar transistor externally coupled, i.e., connected to an external power rail, has a swing of only about 0.8 V between logic level high and logic level low, while an internally-coupled bipolar transistor--that is, one not tied directly to the high-potential or the low-potential power rail--can have a logic level swing as low as 200 mV. A digital circuit having a rail-to-rail voltage differential set between 0.0 V and 5.0 V, for example, would have an externally-coupled bipolar transistor responding to a logic high of about 4.1 V and to a logic low of about 3.3 V. On the other hand, a MOS transistor has logic level swings essentially equal to the rail-to-rail voltage differential, or, for the example provided, logic high would be on the order of 5.0 V and logic low on the order of 0.0 V. Further, the greater capacitance associated with MOS transistors increases the time to achieve this switch, as compared to the switching times associated with bipolar transistors. A relatively-fast-switching circuit having bipolar transistors in an ECL design will have propagation delays of only about 100-150 picoseconds (for one gate)--and an average power dissipation of about 22 mW for an output buffer. A MOS-transistor-based circuit will have propagation delays of about 200-400 picoseconds (again for a single gate) but average power dissipation in the microwatt range. In most cases, MOS devices are much more temperature and process dependent, as well as load dependent. ECL devices, however, are much less sensitive to such variations and are load-independent. It is also to be noted that the power dissipation indicated for MOS transistors is frequency-dependent while for ECL it is not. For this reason, it is to be understood that operation of MOS devices at relatively low frequencies results in less power dissipation than the operation of ECL devices, but that is not usually the case at higher frequencies. The "cross-over" point at which one transistor-type is less dissipative than the other involves many factors including the associated load, the size of the device, and fabrication, among others.
When MOS and bipolar transistors are combined to create fast-switching, low-power circuits, certain compatibility problems have to be addressed. I.e., in BiCMOS circuits, bipolar sub-circuits may receive logic signals and then pass on these signals to MOS sub-circuits. The problem is that the logic levels output from a bipolar transistor are generally insufficient to switch a MOS transistor, as can be seen from the respective high-to-low voltage swings noted above. Hence, there must be provided a circuit for converting bipolar logic-level signals to MOS logic-level signals. This can be done in a straightforward fashion utilizing a translator sub-circuit designed to effect that transition. However, such translators inherently introduce delay; that is, it takes time to switch between bipolar and MOS logic levels using such a supplemental sub-circuit. The problem then is to produce a translator which does not cause a significant propagation time increase.
In the field of BiCMOS circuits one particular type of sub-circuit being used with greater frequency is Emitter-Coupled-Logic (ECL). It is well-known that ECL gates are very fast, primarily because the logic level swing is small and because ECL circuits are biased for current-mode operation, thus ensuring that the transistors are not saturated and that there is no storage delay time. ECL circuits are also used in the translators linking the two types of circuitry in BiCMOS circuits. When the ECL component of the circuit is run as a single-ended device, rather than in a differential mode, problems arise due to the voltage fluctuations (due to pick-up) that the high-potential power rails of all circuits are subject to. One result of such sensitivity is the premature switching of the ECL gate. Of course, when the translator is run differentially, fluctuations in absolute voltage levels are of much less concern than the difference in the level swings. In any event, other fluctuations of notable concern are those associated with temperature swings and manufacturing variations from wafer to wafer as well as on the same wafer.
Prior-art ECL-to-CMOS translators have not effectively addressed all of the various problems noted, including propagation delay and sensitivity to power-rail and temperature fluctuations. The prior-art ECL-to-CMOS translator illustrated in FIG. 1 is a logic-level transition amplifier providing translation between a complementary ECL input stage and a MOS output stage, as described in U.S. Pat. No. 4,864,159 issued to Cornelissen on Sep. 5, 1989. The complementary input pair, Q1 and Q2, are emitter-follower transistors providing output signals to PMOS transistors QP1 and QP2 and to PMOS transistors QP3 and QP4. The gates of the noted PMOS transistors are all connected to the gate of PMOS QP5 through NMOS QN5. It is indicated that NMOS QN5 can be used to isolate QP5 from any transients. There are several problems related to the reference stage of the translator illustrated in FIG. 1. Specifically, the use of PMOS QP5 at the reference output provides significant impedance to switching and therefore, in all likelihood slows the propagation rate of the translator. In addition, the high impedance associated with the use of that transistor minimizes the ability to use that single reference stage to fan out to a plurality of output load stages. Also, while it is indicated that NMOS transistor QN5 can be used as an isolation device, the illustrated circuit nevertheless will remain sensitive to switching noises at the gate of QP5. Finally, the prior-art noted fails to address the need to be able to "tune" the propagation delay as desired.
What is needed therefore, is an ECL-to-CMOS translator circuit that provides: (1) isolation from power-rail-voltage fluctuations, temperature fluctuations, and manufacturing-process effects; (2) minimum, selectable propagation delay with effective isolation from switching noise; and (3) the ability to tune the propagation delay through standard fabrication techniques. Further, what is needed is a translator that provides for multiple translation (fan-out) using a single reference stage. Finally, what is needed is a translator that may be utilized in a variety of situations requiring translation including, but not limited to, phase-lock loops and clock recovery circuits.